1. Field of the Invention
The disclosure relates in general to a method of manufacturing a semiconductor structure, and more particularly to the method of manufacturing the semiconductor structure including a two-step process of filling conductors and performing thermal treatments.
2. Description of the Related Art
TSV (through silicon via) technology is developed for providing interconnection between stacked wafers (chips) in three-dimensional integrated circuit (3D-IC) design. Compared to the conventional stacked IC package, TSV creates a 3D vertical conducting path, and the length of conductive line is reduced to equal the thickness of wafers (chips) substantially, thereby increasing the density of stacked wafers (chips) and enhancing the speed of signal transfer and electrical transmission. Also, parasitic effect can be decreased due to the vertical connection of conductor, so as to lower power consumption. Moreover, TSV technology offers the heterogeneous integration of different ICs (for example; stacking memory on the processor) to achieve the multi-functional integration.
There are various processes using TSV technology for the three-dimensional integration. Those processes can be classified as via-first approach, via-middle approach, and via-last approach according to the forming process in order and final configurations. Whether the process (ex: via-first approach, via-middle approach, or via-last approach) is adopted, the quality of through silicon via filled with conductor has considerable effect on the electrical performance of the stacked wafers (chips).